One of the goals in the fabrication of electrically programmable read only memories (EPROMs) is the production of a memory circuit which is capable of storing a maximum amount of information using a minimum amount of semiconductor surface area. However, photolithographic limits imposed by conventional semiconductor processing technology impede the achievement of this goal. Thus, an inability to pattern and etch semiconductor features closer together prevents a memory cell from occupying a smaller portion of a semiconductor's surface area.
EPROMs often utilize a floating gate avalanche injection MOS (FAMOS) structure to store programmed information. Floating gate dimensions in a FAMOS memory cell are conventionally established with reference to minimum photolithographic limits, and therefore produce undesirably large memory cells.
One solution to this problem of dimensioning a floating gate at minimum photolithographic limits is provided by the use of a sidewall floating gate formed on a sidewall of a control gate. However, since the floating gate is merely added to a sidewall of an ordinary, photolithographically defined control gate, the resulting structure is actually larger than a structure achievable at minimum photolithographic limits. In addition, it provides an undesirably diminished capacitive coupling between the floating gate and the control gate. Accordingly, a need exists for a memory cell in which a floating gate structure is provided with dimensions less than minimum photolithographic limits, but which is not formed on a sidewall of a control gate.